Regviz

Espressif Systems /ESP32-P4 /ISP /FRAME_CFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FRAME_CFG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/ISP/FRAME_CFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VADR_NUM0HADR_NUM0BAYER_MODE 0 (HSYNC_START_EXIST)HSYNC_START_EXIST 0 (HSYNC_END_EXIST)HSYNC_END_EXIST

Description

frame control parameter register

Fields

VADR_NUM

this field configures input image size in y-direction, image row number - 1
HADR_NUM

this field configures input image size in x-direction, image line number - 1
BAYER_MODE

this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB
HSYNC_START_EXIST

this bit configures the line end packet exist or not. 0: not exist, 1: exist
HSYNC_END_EXIST

this bit configures the line start packet exist or not. 0: not exist, 1: exist

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data